Asynchronous latch circuit and register

Details Asynchronous latch circuit and register Asynchronous latch circuit and register

1993-05-21

1995-04-25

Baker, Stephen M.

Excavating

327198, 327218, 326 21, 326 93, G11C 11413, G11C 2900, H03K 5153, H03K 3288

Patent

active

054105501

ABSTRACT:
An asynchronous latch circuit characterized by a pair of D-type flip-flops and a D-type latch. Data is clocked into a first flip-flop by a system clock signal and the output of the first flip-flop is clocked into a second flip-flop by an asynchronous latch enable signal. A comparator compares the outputs of the first and second flip-flops and develops an error signal if the two are not the same. The error signal forces the output of the latch to a known condition rather than letting the output be indeterminate. In an asynchronous latch register an error signal from any one of the asynchronous latch circuits will force all of the latch circuits in the register to a known condition to eliminate race condition errors.

REFERENCES:
patent: 3555255 (1971-01-01), Toy
patent: 3950705 (1976-04-01), Fuerherm
patent: 4999528 (1991-03-01), Keech
patent: 5233617 (1993-08-01), Simmons et al.
Millman, et al., Microelectronics, McGraw-Hill Book Co., 1987, pp. 315, 316, 323, 324.
Stone, Microcomputing Interfacing, 1983, Addison-Wesley Series in Electrical Engineering.

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