Memory integrated circuit with protection against disturbances

Details Memory integrated circuit with protection against disturbances Memory integrated circuit with protection against disturbances

1994-07-14

1995-04-25

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Including signal clamping

36518902, 365154, 365156, 365203, 365205, 36523003, G11C 700

Patent

active

054105064

ABSTRACT:
Disclosed is an integrated circuit memory comprising at least one column of memory cells parallel connected with one another and connected to at least one bit line, each memory cell being connected to a bit line by at least one access transistor, wherein said memory contains a protection transistor that is connected to the bit line and controlled so as to be made conductive so as to limit the voltage drop on the bit line, during the stages of the reading of the memory, when this drop in voltage goes beyond a threshold having a value smaller than a value that prompts the writing of an information element in a memory cell.

REFERENCES:
patent: 4707810 (1987-11-01), Ferrant
patent: 4761767 (1988-08-01), Ferrant
patent: 4879693 (1989-11-01), Ferrant
patent: 4932002 (1990-06-01), Houston
patent: 5023841 (1991-06-01), Akrout et al.
patent: 5034924 (1991-07-01), Taniguchi et al.
patent: 5113372 (1992-05-01), Johnson

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