Discrete cosine transform apparatus and inverse discrete cosine

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364725, 364754, G06F 738

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054105005

ABSTRACT:
Input data of 8 rows and 8 columns are input from an input terminal (IN) in the sequential order of columns and supplied through a first rearranging circuit (41) of 64 words to a 4-degree first inner product calculating circuit (42). An output of this inner product calculating circuit (42) is supplied through a second rearranging circuit (43) of 64 words to an 8 degree second inner product calculating circuit (44). An output of the inner product calculating circuit (44) is supplied to a 4-degree third inner product calculating circuit (45), and an output of the inner product calculating circuit (45) is delivered through a rearranging circuit (46) to an output terminal (OUT). Therefore, the inner product calculating circuit can be reduced in circuit scale, the circuit arrangement can be simplified and the number of calculation can be reduced to thereby enable a high speed calculation to be carried out.

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"IEEE Journal of Solid-State Circuits", vol. 27, No. 4, Apr. 1992, pp. 492 to 498.

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