Multi-bank synchronous memory system with cascade-type memory ce

Details Multi-bank synchronous memory system with cascade-type memory ce Multi-bank synchronous memory system with cascade-type memory ce

1996-07-31

1997-11-18

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

365221, 36523006, 36523009, 365239, G11C 800

Patent

active

056894732

ABSTRACT:
A synchronous memory system with a cascade-type memory cell structure has memory cells having a cascade type construction (or NAND type configuration), a row decoder, save registers, a sense amplifier, and a selector. The selector transmits a control signal to halt a sense operation for the memory cells when the sense operation for a target memory cell to be accessed in completed. The row decoder includes a decoder for decoding a row address, a latch circuit, a word line driver. The latch circuit stores a result of a decode operation, and the word line driver comprises a PMOS transistor and a NMOS transistor connected in series. A 8 volt power (Vpp) is supplied to the PMOS transistor in the word line driver.

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