Semiconductor memory device and defective memory cell correction

Details Semiconductor memory device and defective memory cell correction Semiconductor memory device and defective memory cell correction

1996-08-26

1997-11-18

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 3652257, 371 102, G11C 700, G11C 2900

Patent

active

056894651

ABSTRACT:
To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal.
It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.

REFERENCES:
patent: 5282165 (1994-01-01), Miyake et al.
patent: 5293339 (1994-03-01), Suzuki et al.
patent: 5424986 (1995-06-01), McClure

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