Method for testing semiconductor memory device

Details Method for testing semiconductor memory device Method for testing semiconductor memory device

1980-12-29

1983-05-17

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

371 21, G11C 1300

Patent

active

043843484

ABSTRACT:
A semiconductor memory testing device and testing method comprises an address pattern generator which successively generates an address pattern which specifies the X-Y addresses of each memory cell of a semiconductor memory device which is to be tested, an address changeover or swapping device which makes access to the semiconductor memory device with the address pattern supplied by the address pattern generator during normal operation mode, and addresses interchanged during swap operation mode, a comparator which compares data from the semiconductor memory device with an expected value to detect hardware error, and a fail memory device which stores information concerning the existence hardware error in each of the memory cells of the semiconductor memory device in an address region corresponding to that of the bad cell of the semiconductor memory device. The semiconductor memory device and the fail memory device both receive common X-Y addresses from the address changeover or swapping device. The comparator preheated from comparing by a signal supplied from said fail memory device for the memory cells of the semiconductor memory device corresponding to the memory cells of the fail memory device which have information stored therein indicating the existence of hardware errors.

REFERENCES:
patent: 4183096 (1980-01-01), Cenker

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