Boots – shoes – and leggings
Patent
1995-08-08
1997-10-14
Kim, Kenneth S.
Boots, shoes, and leggings
395391, 395395, 395563, 364748, G06F 938
Patent
active
056780168
ABSTRACT:
A method and apparatus are disclosed for managing the execution of a floating-point store instruction within a data processing system including a memory and a superscalar processor having a number of floating-point registers (FPRs). According to the present invention, multiple instructions are dispatched for execution by the processor, including a floating-point store instruction having as an operand the content of a particular FPR. A determination is made whether the particular FPR is a destination register for results of a second instruction which precedes the store instruction in program order. If so, a determination is made whether the second instruction must complete before subsequent instructions can be successfully dispatched. In response to a determination that the second instruction must be completed prior to successfully dispatching subsequent instructions, the floating-point instruction is cancelled and redispatched after the completion of the second instruction. In response to a determination that the second instruction need not be completed prior to successfully dispatching subsequent instructions, execution of the floating-point store instruction is initiated by computing the destination address within memory into which the operand of the floating-point store instruction is to be stored, thereby minimizing the delay in executing a floating-point store instruction.
REFERENCES:
patent: 3593312 (1971-07-01), Barton et al.
patent: 4458311 (1984-07-01), Clements et al.
patent: 4476537 (1984-10-01), Blau et al.
patent: 4484301 (1984-11-01), Borgerding et al.
patent: 4722068 (1988-01-01), Kuroda et al.
patent: 4785412 (1988-11-01), Tran
patent: 4809212 (1989-02-01), New et al.
patent: 4860240 (1989-08-01), Hartley et al.
patent: 4893268 (1990-01-01), Denman, Jr. et al.
patent: 5133077 (1992-07-01), Karne et al.
patent: 5235533 (1993-08-01), Sweedler
patent: 5268855 (1993-12-01), Mason et al.
patent: 5317526 (1994-05-01), Urano et al.
patent: 5465373 (1995-11-01), Kahle et al.
patent: 5479622 (1995-12-01), Grohoski et al.
patent: 5553256 (1996-09-01), Fetterman et al.
Eisen Lee E.
Golla Robert T.
Olson Christopher H.
Putrino Michael
Davis Michael A.
Dillon Andrew J.
International Business Machines - Corporation
Kim Kenneth S.
Russell Brian F.
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