Semiconductor memory having redundancy memory decoder circuit

Details Semiconductor memory having redundancy memory decoder circuit Semiconductor memory having redundancy memory decoder circuit

1995-10-11

1997-10-14

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523006, G11C 700

Patent

active

056778821

ABSTRACT:
A redundancy decoder circuit includes an output line U which takes an active level when an access address supplied thereto is coincident with a redundant address programmed therein. This circuit further includes a fuse F which is blown to deactivate the decoder or not blown to activate the decoder, a latch circuit latching a level responsive to a blown or not-blown state of the fuse, and a transistor controlled by the latch circuit to forcibly hold the output line at an inactive level when the fuse is blown.

REFERENCES:
patent: 4698494 (1987-10-01), Chen et al.
patent: 4714839 (1987-12-01), Chung
patent: 5381371 (1995-01-01), Haraguchi
patent: 5471426 (1995-11-01), McClure
patent: 5517455 (1996-05-01), McClure et al.

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