Method and apparatus for selectable parallel execution of test o

Details Method and apparatus for selectable parallel execution of test o Method and apparatus for selectable parallel execution of test o

1994-01-03

1995-09-26

Voeltz, Emanuel Todd

Excavating

371 221, 340514, 36492691, 3649402, 324 731, H04B 1700

Patent

active

054539927

ABSTRACT:
The invention permits selectively enabling a plurality of circuits to synchronously enter and execute test operations based on a given test bus. A test bus controller (15) is enabled to simultaneously initiate test operations on two or more selected circuits (17) coupled to the test bus (11) via a connection device (19) and a connection protocol.

REFERENCES:
patent: 4701921 (1987-10-01), Powell et al.
patent: 4860290 (1989-08-01), Daniels et al.
patent: 5054024 (1991-10-01), Whetsel
patent: 5056093 (1991-10-01), Whetsel
patent: 5198759 (1993-03-01), Ohnesorge
Bhavsar, Dilip, "An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes," 1991, IEEE Int'l Test Conf., Paper 28.2 pp. 768-776.

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