Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1990-09-28
1993-12-28
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 371 111, G11C 700
Patent
active
052745937
ABSTRACT:
A semiconductor memory having a redundant column is described in which access time is not reduced when the redundant column is employed to replace a defective column. The memory includes a number of columns of memory cells, each column having a corresponding input/output node. A set of input/output lines, the set typically being one smaller than the number of columns, is connected to a corresponding set of switches. The switches connect each input/output line to one, and only one input/output node chosen in response to a control signal supplied to the switch. By having positioned all of the switches on the left side of the defective column to connect to columns to the left of their respective input/output connections, and by positioning all of the switches on the right side of the defective column to connect to the columns on the right side of their respective input/output connections, the defective column is removed from operation without increase in propagation delays. In this manner, the access speed of the memory remains constant regardless of which column is defective.
REFERENCES:
patent: 5134584 (1992-07-01), Boler et al.
Intergraph Corporation
Popek Joseph A.
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