Plural test mode selection circuit

Details Plural test mode selection circuit Plural test mode selection circuit

1989-05-30

1991-07-30

Wieder, Kenneth A.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324158T, 371 221, G01R 1512

Patent

active

050362720

ABSTRACT:
A plural test mode selection circuit in a semiconductor device capable of extending the number of option modes, e.g., up to 16 option modes by adding a high voltage sensing circuit 15 to any one of a plurality of input pads and by arranging a master decoder 25 and a slave decoder 20 each coupled to a plurality of buffer circuits 11-14, as well as a mode selector 30 and a plurality of address/control pads 5-9, and then an output of a high voltage sensing circuit 15 and respective outputs of the master decoder 25 and a slave decoder 20 are combined together at a mode selector 30, so that a plurality of test modes selection is possible therefrom. In addition, the invention also has an advantage capable of testing a chip even after it has been made into a package because of utilizing the address/control pad used in a general read/write operation.

REFERENCES:
patent: 4336495 (1982-06-01), Hapki
patent: 4398146 (1983-08-01), Draheim et al.
patent: 4743841 (1988-05-01), Takeuchi
patent: 4752729 (1988-06-01), Jackson et al.
patent: 4825439 (1989-04-01), Sakashita et al.
patent: 4833395 (1989-05-01), Sasaki et al.
patent: 4841233 (1989-06-01), Yoshida
patent: 4866714 (1989-09-01), Adams et al.
patent: 4910735 (1990-03-01), Yamashita

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