Method of manufacturing schottky barrier gate type fet

Details Method of manufacturing schottky barrier gate type fet Method of manufacturing schottky barrier gate type fet

1992-09-04

1995-04-11

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437174, 437175, 437177, 437184, 437192, 437247, 437912, H01L 21306, H01L 2144

Patent

active

054057922

ABSTRACT:
The method of manufacturing the SB FET according to the present invention includes a first step of forming a refractory metal film on a semiconductor substrate, a second step of forming a first ion-implanted region within the semiconductor substrate, by an ion implantation process, a third step, independent of the second step, of forming second and third ion implantation regions in the semiconductor substrate by an ion implantation process during which impurity ions pass through the first film, with the second and third ion implantation regions being adjacent to the first ion implanted region. A fourth step of forming a channel region, source region and drain region by annealing to activate said first, second, and third ion implanted regions using the first film as a protective film, and bringing the first film in Schottky contact with the channel region, a fifth step of forming a Schottky gate electrode in Schottky contact with the channel region by patterning the first film after the channel, source and drain regions have been formed, with the first film being selectively maintained to prevent exposure of the channel region underlying the Schottky gate electrode, and a sixth step of forming a second film made of a refractory metal or a refractory metal compound on the first film forming a portion of said Schottky gate electrode.

REFERENCES:
patent: 4330343 (1982-05-01), Christou et al.
patent: 4546540 (1985-10-01), Ueyanagi et al.
patent: 4581076 (1986-04-01), Badawi
patent: 4601095 (1986-07-01), Kikuchi et al.
patent: 4636822 (1987-01-01), Codella et al.
patent: 4642879 (1987-02-01), Kawata et al.
patent: 4729966 (1988-03-01), Koshino et al.
patent: 4735913 (1988-04-01), Hayes
patent: 4929567 (1990-05-01), Park et al.
patent: 5143856 (1992-09-01), Iwasaki
patent: 5187111 (1993-02-01), Nogami et al.
Onodera et al., "A High-Transconductance Self-Aligned GaAs MESFET Fabricated by Through-AIN Implantation," IEEE Transactions on Electron Devices, vol. ED-31, No. 12, pp. 1808-1813, Dec. 1984.
Katsuhara, "Analysis of Implantation Through Insulating Film/GaAs by Boltzmann Transport Equation," Applied Physics Institute, Academic Written Lecture, Spring 1985, 30a-X-s; NEC; Apr. 1985.
Japanese Patent Disclosure (KOKAI) No. 61-42963 filed Aug. 6, 1984; Disclosed Mar. 1, 1986, Inventors: M. Kanamori et al., "Method of Producing Semiconductor Device".
Gallium Arsenide Materials, Devices, and Circuits 216 (M. J. Howes and D. V. Morgan, eds., 1985).
H. M. Levy et al., "Self-Aligned Submicron Gate Digital GaAs Integrated Circuits" IEEE Electron Device Letters, vol. EDL-4, No. 4, Apr., 1983.

Affiliated with

Also associated with

Rating

Method of manufacturing schottky barrier gate type fet does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing schottky barrier gate type fet, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing schottky barrier gate type fet will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1538124