Semiconductor memory device incorporating a test mechanism

Details Semiconductor memory device incorporating a test mechanism Semiconductor memory device incorporating a test mechanism

1995-11-01

1997-06-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518907, 3652257, G11C 700, G11C 2900

Patent

active

056423179

ABSTRACT:
To present a semiconductor memory device incorporating a test mechanism in order to test plural semiconductor memory devices by using a tester having a single data judging circuit. The drain electrode of an N type MOSFET (Q16) is connected to a power source potential (V.sub.CC) through a fuse element (F1) (route cut-off element), and the source electrode is connected to the drain electrode of an N type MOSFET (Q17), and the drain electrode of the N type MOSFET (Q16) is connected to the input of an inverter (G16), and is also connected to a resistance element (R1) connected to a grounding potential (V.sub.SS). Therefore, since the test mechanism is incorporated, parallel tests are conducted by the inexpensive tester having only one data judging circuit, and thereafter by judging the results of comparison individually by using the same tester, the qualification of the semiconductor memory device can be judged.

REFERENCES:
patent: 536869 (1895-07-01), Yoshida
patent: 5404332 (1995-04-01), Sato et al.
1987 IEEE International Solid-State Circuits Conference, pp. 286-287, Feb. 27, 1987, T. Ohsawa, et al., "FAM 20.9: A 60ns 4Mb CMOS DRAM With Built-In-Self-Test".
1992 IEEE International Solid-State Circuits Conference, pp. 150-151, Feb. 20, 1992, H. Koike, et al., "TP 9.2: A 30ns 64Mb DRAM With Built-In Self-Test and Repair Function".

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