Semiconductor memory device with address transition actuated dum

Details Semiconductor memory device with address transition actuated dum Semiconductor memory device with address transition actuated dum

1989-06-23

1991-08-13

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

365207, 365208, 365210, 3652335, G11C 700, G11C 11407, G11C 11413, G11C 1606

Patent

active

050401483

ABSTRACT:
In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

REFERENCES:
patent: 4761765 (1988-08-01), Hashimoto
patent: 4802138 (1989-01-01), Shimamune
patent: 4805143 (1989-02-01), Matsumoto et al.
patent: 4819212 (1989-04-01), Nakai et al.
patent: 4884241 (1989-11-01), Tanaka et al.
"A 55ns 64K.times.16b CMOS EPROM" by M. Kukuda et al., ISSCC Digest Technical Papers, 1988 IEEE International Solid-State Circuit Conference, Feb. 1988, pp. 122-123.
"A 90ns 4Mb CMOS EPROM" by G. Canepa et al., ISSCC Digest of Papers, 1988 IEEE International Solid-State Circuits Conference, Feb. 1988, pp. 120-121.
"E-PROMs Graduate to 256-K Density with Scaled n-Channel Process", M. Van Buskirk et al., Electronics, Feb. 24, 1983, p. 89.

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