Semiconductor memory device having test mode

Details Semiconductor memory device having test mode Semiconductor memory device having test mode

1991-08-14

1993-04-20

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

36518905, 365193, G11C 2900

Patent

active

052048373

ABSTRACT:
A DRAM includes a test mode controller generating a test mode designating signal designating a test mode at a fall of an external control signal RAS when the logical levels of external control signals CAS and WE are low, and a power-on reset circuit responsive to a power supply for generating a reset pulse for resetting main circuits for data reading and data writing. Each of the external control signals CAS and WE are supplied to the test mode controller and the main circuits through a buffer circuit. A first buffer circuit for supplying the external control signal RAS to the test mode controller is provided separately from a second buffer circuit for supplying the external control signal RAS to the main circuits. The second buffer circuit receives the output of the power-on reset circuit and the external control signal RAS to buffer the control signal RAS only when no reset pulse is generated. The first buffer circuit receives only the external control signal RAS to continuously buffer the same without being affected by a reset pulse.

REFERENCES:
patent: 4132937 (1992-07-01), Tuda et al.
patent: 4933902 (1990-06-01), Yamada et al.
patent: 5016220 (1991-05-01), Yamagata
patent: 5051995 (1991-09-01), Tobita
patent: 5073874 (1991-12-01), Yamada et al.
patent: 5088063 (1992-02-01), Matsuda et al.
patent: 5157630 (1992-10-01), Suwa et al.

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