Method of isolating semiconductor devices and arrays of memory i

Details Method of isolating semiconductor devices and arrays of memory i Method of isolating semiconductor devices and arrays of memory i

1993-06-09

1994-03-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 60, 148DIG50, H01L 21304

Patent

active

052926834

ABSTRACT:
A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regions of moat volume into the substrate to define source/drain regions adjacent the field effect transistor gates. The invention also includes an array of memory integrated circuitry.

REFERENCES:
patent: 5057444 (1991-10-01), Fuse et al.
patent: 5112772 (1992-05-01), Wilson et al.
patent: 5229316 (1993-07-01), Lee et al.
patent: 5250456 (1993-10-01), Bryant

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