Method and apparatus for mapping the memory system of a computer

Details Method and apparatus for mapping the memory system of a computer Method and apparatus for mapping the memory system of a computer

1996-12-27

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711170, 711173, 707205, 707206, G06F 1200

Patent

active

058601422

ABSTRACT:
A computer system including a host bus, a processor that asserts addresses between a lowest address and a highest address, at least one peripheral component interconnect (PCI) bus coupled to the host bus, at least one PCI device coupled to the PCI buses, and system memory devices that are mapped between the lowest address and an upper system memory address defined by PCI memory. Each PCI device has memory that is mapped in reverse and descending order in the PCI memory, which is located between a predetermined upper PCI memory address and the upper system memory address below the upper PCI memory address. The determination of the upper system memory through the reverse and descending mapping enables increased usage of system memory. The PCI devices coupled through each host PCI bus and its corresponding subordinate PCI buses are mapped together, resulting in a segment in the PCI memory for each host PCI bus. Further, for each host PCI bus and its subordinate PCI buses, if any, the non-prefetchable memory is grouped together and then the prefetchable memory is grouped together resulting in two sections within each segment. Such mapping provides efficient mapping of PCI devices, resulting in even greater usage of system memory.

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patent: 5649127 (1997-07-01), Hang
patent: 5668968 (1997-09-01), Wu
patent: 5717876 (1998-02-01), Robertson

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