System for using a dirty bit with a cache memory

Details System for using a dirty bit with a cache memory System for using a dirty bit with a cache memory

1996-06-03

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711142, 711143, 711145, G06F 1200

Patent

active

058601139

ABSTRACT:
A system for writing to a cache memory which eliminates the need, in certain circumstances, to set a dirty bit. The dirty bit indicates that the line of data in the cache has been updated but the corresponding data in main memory has not been updated. Setting the dirty bit can increase the time needed for a bus cycle. When a line of data is written to a cache memory, a dirty bit is set for that line of data. If the next bus cycle is a write to the cache for the same line of data, the cache controller can save time by not setting the dirty bit because the cache controller knows that the dirty bit has been previously set.

REFERENCES:
patent: 4939641 (1990-07-01), Schwartz et al.
patent: 5420994 (1995-05-01), King et al.
patent: 5537575 (1996-07-01), Foley et al.
patent: 5553266 (1996-09-01), Metzger et al.

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