Built-in test scheme for a jitter tolerance test of a clock and

Details Built-in test scheme for a jitter tolerance test of a clock and Built-in test scheme for a jitter tolerance test of a clock and

1996-03-04

1998-11-10

Chung, Phung M.

Excavating

371 1, 371 61, G06F 1100

Patent

active

058355014

ABSTRACT:
A jitter test system for a clock and data recovery unit (CRU) is comprised of a data generating apparatus, apparatus for clocking the data generating apparatus with a jittered clock, apparatus for applying a stream of data generated by the data generating apparatus that has been jittered by the jittered clock to an input of the CRU, and apparatus for detecting a bit error rate of a data signal output from the CRU.

REFERENCES:
patent: 4916411 (1990-04-01), Lymer
patent: 5239535 (1993-08-01), Borm et al.
patent: 5515404 (1996-05-01), Pearce

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