Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-02-27
1998-11-10
Nguyen, Tan T.
Static information storage and retrieval
Read/write circuit
Testing
371 212, G11C 2900
Patent
active
058354280
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method of testing a semiconductor memory such as a RAM (random access memory), a ROM (read only memory), a charge transfer device (CCD) memory or the like and to an apparatus for carrying out the method. Particularly, the present invention relates to a method of testing a semiconductor memory by which a failure history of the tested memory can be smoothly read from a failure analysis memory, and to an apparatus for carrying out the method, the failure history being the stored contents of a failure analysis memory which stores the test results (the results of pass/failure decision) of a semiconductor memory.
BACKGROUND ART
First, a basic arrangement of a conventional semiconductor memory testing apparatus of this type will briefly be explained with reference to FIG. 12. The illustrated semiconductor memory testing apparatus comprises a timing generator 1, a test pattern generator 2, a waveform shaping device 3, a logical comparator 4 and a failure analysis memory 5, and carries out a testing of a semiconductor memory 6 to be tested. The test pattern generator 2, in response to a reference clock (REF CLK) CK supplied from the timing generator 1, generates an address signal ADS, a test data signal PD and a control signal (CONT SIG) CS to be supplied to the memory 6 under test (MUT) as well as generates an expected value (EXP) data signal ED to be supplied to the logical comparator 4 and the failure analysis memory 5. These signals (data) ADS, PD and CS are inputted to the waveform shaping device 3 where the signals are shaped in waveform to be required for the testing of the memory 6 under test, and then are applied to the memory 6.
The memory 6 under test is controlled in writing or reading of a test data signal thereto or therefrom by application of a control signal CS thereto. That is, a test data signal is sequentially written to the address of the memory 6 under test specified by an address signal ADS by applying a control signal CS for writing to the memory 6. On the contrary, a test data signal written in the memory 6 under test is sequentially read out from the address thereof specified by an address signal ADS by applying a control signal CS for reading to the memory 6. A read out data signal RD read from the memory 6 under test is supplied to the logical comparator 4 in which the read out data signal RD is compared with an expected value data signal ED outputted from the test pattern generator 2. Then, a decision of pass or failure for the memory 6 under test (PASS/FAIL DECISION) is rendered based on the comparison result, i.e., on the basis that the read out data signal is conformable or unconformable to the expected value data signal.
The failure analysis memory 5 used in the semiconductor memory testing apparatus stores a sequence data which is outputs of the test pattern generator 2 in a cycle in which the result of a pass/failure decision for a memory under test is failure. That is, the failure analysis memory 5 stores an address signal ADS, a test data signal PD, an expected value data signal ED and failure information indicating a state of a data output pin or pins of the memory 6 under test which is decided to be a failure. After the test is completed, a failure analysis of the memory 6 under test is performed by reading and analyzing the stored contents of the failure analysis memory 5.
In the conventional semiconductor memory testing apparatus mentioned above, an address signal ADS, a test data signal PD and a control signal CS generated by one-test pattern generator 2 are applied to a memory 6 under test and failure data of the memory 6 is stored in corresponding one failure analysis memory 5. Therefore, when the sequence data and the failure information in a cycle in which the result of a pass/failure decision for a memory 6 under test is failure are stored in the failure analysis memory 5, the only data in the cycle in which the result of a pass/failure decision for the memory 6 is failure may be stored in the failure analysis memor
REFERENCES:
patent: 5278839 (1994-01-01), Matsumoto et al.
patent: 5291449 (1994-03-01), Dehara
patent: 5539699 (1996-07-01), Sato et al.
patent: 5673270 (1997-09-01), Tsujimoto
Advantest Corporation
Nguyen Tan T.
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