Memory management in fault tolerant computer systems utilizing a

Details Memory management in fault tolerant computer systems utilizing a Memory management in fault tolerant computer systems utilizing a

1996-07-01

1999-09-14

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711163, 711167, 395181, 39518203, 39518209, G06F 1300, G06F 1100

Patent

active

059537426

ABSTRACT:
A memory management system for a fault tolerant computer system. The memory management system includes a first recording mechanism which can be activated to record memory update events; a second recording mechanism which records at least a limited number of memory update events; a fault input for a fault signal to activate the first recording mechanism in the event of a fault event; and a memory reintegration mechanism to reintegrate at least parts of memory identified in the first and second recording mechanisms. Preferably, the recording of memory updates (writes) is not based on recording each address accessed, but rather on memory segments (pages) updated (written to). Further, a fault tolerant computer system includes a plurality of synchronous processing sets, each having a processor with internal memory and operating in lockstep, and an out of sync detector for detecting an out-of-sync-event and for generating an out-of-sync signal.

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