Memory having error detection and correction

Details Memory having error detection and correction Memory having error detection and correction

1997-09-29

1999-09-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

371 30, 371 4011, 371 402, G11C 700

Patent

active

059532653

ABSTRACT:
A memory system having: a plurality of memory packages for storing words, each one of the packages being adapted to store a plurality of different bits of the word; and an error detection and correction system adapted to detect an error produced in any one of the packages in storing the digital word. With such an arrangement, an error produced by a defect in one of plurality of memory packages, each adapted to store more than one bit of a digital word, may be corrected without requiring changes to other EDACs used in a system employing such memory system. The memory system has a buffer for storing a digital word having N bits of data and M redundant bits for error detection and correction. An error correction code generator is provided for converting the digital word into a second digital word having N bits of data and P redundant bits for error detection and correction. A memory is used for storing the N+P digital word. A error correction code detector corrects an error the data read from the memory.

REFERENCES:
patent: 4768193 (1988-08-01), Takemae
patent: 5179536 (1993-01-01), Kasa et al.
patent: 5577004 (1996-11-01), Leshem
patent: 5671239 (1997-09-01), Higashitani et al.

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