Simultaneous deposit and etch method for forming a void-free and

Details Simultaneous deposit and etch method for forming a void-free and Simultaneous deposit and etch method for forming a void-free and

1996-04-01

1999-01-12

McCamish, Marion

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438697, 438712, 438723, 427585, H01L 2102

Patent

active

058588760

ABSTRACT:
A method for forming a void-free and gap-filling doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit. Formed upon a semiconductor substrate is a patterned substrate layer. Formed upon the patterned substrate layer is a doped silicon oxide insulator layer. The doped silicon oxide insulator layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method. The Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employ a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.

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Korczynski et al, "Improved Sub-Micron Inter-Metal Dielectric Gap-Filling Using Teoslozone APCVD" Microelectronics Manufacturing Technology, Jan. 1992, pp. 22-27.

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