Memory input data test arrangement

Details Memory input data test arrangement Memory input data test arrangement

1989-08-09

1991-12-31

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Testing

36518903, 36518908, 36518905, 36518907, 36523008, G11C 2900, G11C 700

Patent

active

050776908

ABSTRACT:
A memory system in which the input/output circuitry can be tested independently from the storage cells and decoder therein by permitting a write operation, with information at the memory inputs being provided to the memory outputs as well as to the storage cells.

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patent: 4811294 (1989-03-01), Kobayashi et al.
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"Functional and Level Fail Detection for Register Array Testing," P. Heavey et al, IBM Technical Disclosure Bulletin, vol. 15, No. 4, 9/72, pp. 1135-1136.
"Clock and Counter Hardware Compose Static RAM Chip Tester That Writes, Reads, and Validates Test Data Patterns for Different Memory Organizations by Modifying Counter Bit Lengths and Clock Phases," A. Bently, Computer Design, 6/79, pp. 124-136.
"Test Catches RAM Errors at Max Speed," M. Stofka, Design Ideas, EDN, vol. 26, No. 8, 4/15/81, pp. 150, 152.

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