Memory device with improved charge storage barrier structure

Details Memory device with improved charge storage barrier structure Memory device with improved charge storage barrier structure

1997-10-28

1999-09-14

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257324, 257411, H07L 2906

Patent

active

059526920

ABSTRACT:
A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si.sub.3 N.sub.4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

REFERENCES:
patent: 3878549 (1975-04-01), Yamazaki et al.
patent: 5216262 (1993-06-01), Tsu
patent: 5286994 (1994-02-01), Ozawa et al.
patent: 5319229 (1994-06-01), Shimoji et al.
patent: 5604357 (1997-02-01), Hori
IEEE Transactions on Electron Devices, vol. 41, No. 9, Sep. 1994, pp. 1628-1638, K. Yano et al.: Room-Temperature Single-Electron Memory.
1996 IEEE International Solid-State Circuits Conference, pp. 266-268, K. Yano, et al.: Single-Electron-Memory Integrated Circuit for Giga-to-Tera Bit Storage.
Appl. Phys. Lett. 68 (10), Mar. 4, 1996, pp. 1377-1379, Sandip Tiwan et al.: A Silicon Nanocrystals-based Memory.
IEEE Electron Device Letters, vol. EDL 1, No. 9, Sep. 1980, pp. 179-181, DiMaria et al.: Electrically-Alterable Memory Using A Duel Electron Injector Structure.
IEEE Transactions on Electron Devices, vol. 43, No. 9, Sep. 1996, pp. 1553-1558, Hanati et al.; Fast and Long Retention-Time Nano-Crystal Memory.
Microelectronic Engineering, vol. 32, No. 1/04, Sep. 1996, pp. 297-315, H. Ahmed et al.: Single-Electron Devices.
Physical Review, B. Condensed Matter, vol. 50, No. 12, Sep. 15, 1994, pp. 8961-8964, Bar-Sadeh et al.: Single-Electron Tunneling Effects in Granular Metal Films.

Affiliated with

Also associated with

Rating

Memory device with improved charge storage barrier structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device with improved charge storage barrier structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device with improved charge storage barrier structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1512419