Integrated semiconductor memory

Details Integrated semiconductor memory Integrated semiconductor memory

1985-12-20

1988-05-03

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

371 21, G11C 700

Patent

active

047424907

ABSTRACT:
Integrated semiconductor memory includes n identical memory cell fields, each having a data width equal to m, n . m data lines for writing-in and reading-out memory data into and out of the memory cell fields, m first data separators each having an assigned data input terminal for applying the memory data as a function of addressing data when written-in, m second data separators for selecting one of the n data lines in response to the addressing data when reading out the memory data and for applying the memory data to the outputs of the second data separators, data output terminals for receiving the memory data, evaluation circuits connected to data lines for feeding data to the data output terminals in response to a control signal for activating an error signal to the data output terminals upon the occurrence of faulty memory data, third data separators for transferring the memory data in parallel to all of the n data lines in response to the control signal, and fourth data separators for selectively feeding either the memory data selected by the second data separators or the output signal generated by the evaluation circuit to the data output terminals in response to the control signal.

REFERENCES:
patent: 4541090 (1985-09-01), Shiragasawa
S. Eaton et al., "A 100 ns 64K Dynamic RAM using Redundancy Techniques", 1981 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, Feb. 1981, pp. 84-85.
Publication Elektronik, No. 15, Jul. 30, 1982, pp. 27-30, P. Mattos et al., "Nibble-Mode beschleunigt Speicherzugriff".
Patents Abstracts of Japan, vol. 6, (P-111), (940), No. 62, Apr. 1982.

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