Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1999-02-19
2000-07-04
Shin, Christopher B.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
36518902, 36523002, 365233, 710 3, 710 9, 710 36, 710 51, 710 61, 710129, G06F 1300
Patent
active
060852844
ABSTRACT:
A method of operating a synchronous memory device, wherein the memory device includes a plurality of memory cells and a register for storing an identification value which identifies the memory device on a bus. Block size information is provided to the memory device, wherein the block size information specifies an amount of data to be output onto a bus in response to a read request. The read request is issued to the memory device, and includes identification information, wherein in response to the read request, the memory device determines whether the identification information corresponds to the identification value stored in the register. When the identification information corresponds to the identification value, the memory device outputs an amount of data corresponding to the block size information onto the bus synchronously with respect to at least a first external clock. The memory device may further include a programmable register. An access time value may be provided to the memory device wherein, in response, the memory device stores the access time value in the programmable register. Here, the access time value is representative of a delay to transpire before data is output onto the bus in response to the read request.
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Farmwald Michael
Horowitz Mark
Rambus Inc.
Shin Christopher B.
Steinberg Neil A.
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