Adjustable output driver circuit

Electronic digital logic circuitry – Interface – Current driving

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326 27, 326 83, H03K 190185

Patent

active

060844345

ABSTRACT:
An output driver circuit offers wave-shaping and logic level adjustment for high speed data communications in a synchronous memory such as a dynamic random access memory (DRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Wave-shaping functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different wave-shaping, characteristics of the output signal.

REFERENCES:
patent: 4096402 (1978-06-01), Schroeder et al.
patent: 4183095 (1980-01-01), Ward
patent: 4404474 (1983-09-01), Dingwall
patent: 4638187 (1987-01-01), Boler et al.
patent: 4758743 (1988-07-01), Dehganpour et al.
patent: 4789796 (1988-12-01), Foss
patent: 4829199 (1989-05-01), Prater
patent: 4888498 (1989-12-01), Kadakia
patent: 4958088 (1990-09-01), Farah-Bakhsh et al.
patent: 4961010 (1990-10-01), Davis
patent: 4984204 (1991-01-01), Sato et al.
patent: 4992676 (1991-02-01), Gerosa et al.
patent: 5001369 (1991-03-01), Lee
patent: 5111075 (1992-05-01), Ferry et al.
patent: 5122690 (1992-06-01), Bianchi
patent: 5128560 (1992-07-01), Chern et al.
patent: 5128563 (1992-07-01), Hush et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5150186 (1992-09-01), Pinney et al.
patent: 5165046 (1992-11-01), Hesson
patent: 5179298 (1993-01-01), Hirano et al.
patent: 5194765 (1993-03-01), Dunlop et al.
patent: 5220208 (1993-06-01), Schenck
patent: 5220209 (1993-06-01), Seymour
patent: 5239206 (1993-08-01), Yanai
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5274276 (1993-12-01), Casper et al.
patent: 5276642 (1994-01-01), Lee
patent: 5278460 (1994-01-01), Casper
patent: 5281865 (1994-01-01), Yamashita et al.
patent: 5311481 (1994-05-01), Casper et al.
patent: 5321368 (1994-06-01), Hoelzle
patent: 5347177 (1994-09-01), Lipp
patent: 5347179 (1994-09-01), Casper et al.
patent: 5349247 (1994-09-01), Hush et al.
patent: 5355391 (1994-10-01), Horowitz et al.
patent: 5361002 (1994-11-01), Casper
patent: 5367205 (1994-11-01), Powell
patent: 5400283 (1995-03-01), Raad
patent: 5428311 (1995-06-01), McClure
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5438545 (1995-08-01), Sim
patent: 5440260 (1995-08-01), Hayashi et al.
patent: 5451898 (1995-09-01), Johnson
patent: 5457407 (1995-10-01), Shu et al.
patent: 5473575 (1995-12-01), Farmwald et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5488321 (1996-01-01), Johnson
patent: 5497127 (1996-03-01), Sauer
patent: 5498990 (1996-03-01), Leung et al.
patent: 5506814 (1996-04-01), Hush et al.
patent: 5508638 (1996-04-01), Cowles et al.
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5568077 (1996-10-01), Sato et al.
patent: 5574698 (1996-11-01), Raad
patent: 5576645 (1996-11-01), Farwell
patent: 5578941 (1996-11-01), Sher et al.
patent: 5581197 (1996-12-01), Motley et al.
patent: 5589788 (1996-12-01), Goto
patent: 5590073 (1996-12-01), Arakawa et al.
patent: 5602494 (1997-02-01), Sundstrom
patent: 5619473 (1997-04-01), Hotta
patent: 5621340 (1997-04-01), Lee et al.
patent: 5621690 (1997-04-01), Jungroth et al.
patent: 5627780 (1997-05-01), Malhi
patent: 5627791 (1997-05-01), Wright et al.
patent: 5631872 (1997-05-01), Naritake et al.
patent: 5636163 (1997-06-01), Furutani et al.
patent: 5636173 (1997-06-01), Schaefer
patent: 5636174 (1997-06-01), Rao
patent: 5638335 (1997-06-01), Akiyama et al.
patent: 5644252 (1997-07-01), Watarai
patent: 5661416 (1997-08-01), Takada et al.
patent: 5668763 (1997-09-01), Fujioka et al.
patent: 5694065 (1997-12-01), Hamasaki et al.
patent: 5838177 (1998-11-01), Keeth
Descriptive literature entitled, "400MHz SLDRAM, 4M.times.16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation," SLDRAM Consortium Advance Sheet, published throughout the United States, pp. 1-22.
"Draft Standard for a High-Speed Memory Interface (SyncLink)," Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronic Engineers, Inc. New York, NY, pp. 1-56.
Chapman, J. et al., "A Low-Cost High-Performance CMOS Timing Vernier for ATE", IEEE International Test Conference, Paper 21.2, 1995, pp. 459-468.
Ljuslin, C. et al., "An Intregrated 16-channel CMOS Time to Digital Converter", IEEE Nuclear Science Symposium & Medical Imaging Conference Record, vol. 1, 1993, pp. 625-629.
Taguchi, M. et al., "A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture", IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1493-1497.

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