Electrostatic discharge protective circuit for semiconductor dev

Details Electrostatic discharge protective circuit for semiconductor dev Electrostatic discharge protective circuit for semiconductor dev

1999-03-05

2000-07-04

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

H01L 2701, H01L 2712

Patent

active

060842725

ABSTRACT:
An electrostatic discharge protective circuit including a semiconductor substrate, an input/output pad formed on the semiconductor substrate, a PMOS transistor formed on the semiconductor substrate and having a drain connected to the input/output pad, a first n+ diffusion layer formed in the semiconductor substrate and separated from the drain of the PMOS transistor at a predetermined interval while being connected to a Vcc terminal, a deep n+ diffusion layer formed between the drain of the PMOS transistor and the first n+ diffusion layer, an NMOS transistor formed on the semiconductor substrate and having a drain connected to the input/output pad, and second n+ diffusion layers formed around the NMOS transistor in the semiconductor substrate and connected to a Vss terminal.

REFERENCES:
patent: 5144518 (1992-09-01), Miyazake
patent: 5545909 (1996-08-01), Williams et al.
C. Duvvury et al.; "Output ESD Protection Techniques for Advanced CMOS Process"; 1998 EOS/ESD Symposium Proceedings pp. 206-211.

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