Static timing analyzer and analyzing method for semiconductor in

Details Static timing analyzer and analyzing method for semiconductor in Static timing analyzer and analyzing method for semiconductor in

1996-09-12

2000-07-04

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

G06F 1750

Patent

active

060832738

ABSTRACT:
A circuit is constructed on transistor level out of a net list and it is determined if the output node of a circuit for receiving a clock signal can go to a high impedance state from this circuit. If the output node can go to a high impedance state, it is designated as the starting point for a path searching operation and an input node of the circuit not receiving a clock signal is designated as the terminating point of the path searching operation. If, on the other hand, the output node cannot go to a high impedance state, the output node is designated as the clock node and an input node of the circuit not receiving a clock signal is designated as the terminating point of the path searching operation. With this arrangement, a sequential circuit can be divided into combinational circuits for certain.

REFERENCES:
patent: 5452239 (1995-09-01), Dai et al.
patent: 5598344 (1997-01-01), Dangelo et al.
patent: 5608645 (1997-03-01), Spyrou
patent: 5740347 (1998-04-01), Avidan

Affiliated with

Also associated with

Rating

Static timing analyzer and analyzing method for semiconductor in does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Static timing analyzer and analyzing method for semiconductor in, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Static timing analyzer and analyzing method for semiconductor in will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1482052