Semiconductor memory device capable of relieving defective bits

Details Semiconductor memory device capable of relieving defective bits Semiconductor memory device capable of relieving defective bits

1989-09-11

1992-03-17

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

365227, G11C 700, G11C 2900

Patent

active

050974483

ABSTRACT:
A memory cell array includes static memory cells arranged in an array of n rows.times.m columns. Each of the memory cells includes MOS transistors formed in a semicondutor substrate and in a corresponding one of well regions of the conductivity type opposite to that of the semiconductor substrate. The well regions are independently formed for each row or for every two or more rows of the memory cell array. The well regions are connected to the respective sources of MOS transistors formed in the well regions. The source and backgate of each of the MOS transistors formed in the well regions are connected to the common source wirings for each of the independently formed well regions. Isolation circuits are respectively connected between the common source wirings for the repective well regions and the power source. A row of the memory cell array to which a defective memory cell is connected is isolated from the power source by means of the isolation circuits.

REFERENCES:
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patent: 4685086 (1987-08-01), Tran
patent: 4780851 (1988-10-01), Kurakami
patent: 4858182 (1989-08-01), Pang et al.
IBM Technical Disclosure Bulletin, vol. 25, No. 6, Nov. 1982, CMOS Static Random-Access Memory Layout, J. A. Hiltebeitel, pp. 3120-3122.

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