Optimizing and operating a time multiplexed programmable logic d

Details Optimizing and operating a time multiplexed programmable logic d Optimizing and operating a time multiplexed programmable logic d

1995-08-18

1998-06-02

Teska, Kevin J.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 40, 326 41, H03K 19177

Patent

active

057614830

ABSTRACT:
A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the physical resources include configurable logic elements), determining an appropriate micro cycle for each configurable logic element in the design, placing the resources on the PLD, and connecting the resources. Optimizing the design may include reducing the number of look up tables or reducing the logic depth of the look up tables. If the configurable logic elements include sequential logic elements, then the optimizing step includes rescheduling the sequential logic elements. A method of operating a time multiplexed PLD in a logic engine mode includes programming the PLD to implement a design in stages, wherein each stage is one configuration, sequencing the PLD through all the configurations, and storing the results of the logic performed in one configuration in a plurality of micro registers for use in subsequent configurations. In one embodiment, the PLD includes a plurality of combinational elements and sequential logic elements, wherein the values stored by the sequential logic elements are stored in the micro registers.

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