Method and apparatus for transferring test data from a memory ar

Details Method and apparatus for transferring test data from a memory ar Method and apparatus for transferring test data from a memory ar

1997-06-13

2000-01-11

Hua, Ly V.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714160, 714718, 365201, 36518905, G11C 800

Patent

active

060147598

ABSTRACT:
A memory device includes an output data path that uses single-ended data in conjunction with a flag signal. The output data path transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern if the data does not match the desired pattern outputs the flag signal. The flag signal is input to the output buffer and the output buffer outputs a tri-state condition on the data bus. Since the flag signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

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