Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-01-21
2000-01-11
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711134, 711142, 711143, 711144, 711145, 711206, G06F 1200
Patent
active
060147288
ABSTRACT:
A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclusive. The cache block status field controls whether the cache control unit operates in a write-through write mode or in a copy-back write mode when a write hit access to the block occurs. The cache block status field may be updated by either a TLB write policy field contained within a translation look-aside buffer entry which corresponds to the page of the access, or by a second input independent of the TLB entry which may be provided from the system on a line basis.
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Advanced Micro Devices , Inc.
Kivlin B. Noel
Thai Tuan V.
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