Semiconductor device having laminated source and drain regions a

Details Semiconductor device having laminated source and drain regions a Semiconductor device having laminated source and drain regions a

1998-09-22

2000-01-11

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257458, H01L 2701, H01L 2712, H01L 310392

Patent

active

060139307

ABSTRACT:
A bottom-gate-type semiconductor device comprising crystalline semiconductor layers, in which the source/drain regions each have a laminate structure comprising a first conductive layer (n.sup.+ layer), a second conductive layer (n.sup.- layer) of which the resistance is higher than that of the first conductive layer, and an intrinsic or substantially intrinsic semiconductor layer (i-layer). In this, the n.sup.- layer functions as an LDD region, and the i-layer functions as an in-plane offset region. The semiconductor device has high reliability and high reproducibility, and is produced in a simple process favorable to mass-production.

REFERENCES:
patent: 5825050 (1998-10-01), Hirakawa
"Fabrication of Low-Temperature Bottom-Gate Poly-Si TFTs on Large-Area Substrate by Linear-Beam Excimer Laser Crystallization and Ion Doping Method" H. Hayashi et al., IEDM95, pp. 829-832, 1995.

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