System and method to reduce phase offset and phase jitter in pha

Details System and method to reduce phase offset and phase jitter in pha System and method to reduce phase offset and phase jitter in pha

1996-01-26

1998-03-10

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375374, 375375, H03D 324

Patent

active

057270376

ABSTRACT:
A system and method for using self-biased circuits to reduce phase jitter and phase offset in phase locked loops and frequency is disclosed. A self-biased apparatus for aligning a reference signal having reference phase with a feedback signal having a feedback phase includes a phase-frequency detector for comparing the reference phase and the feedback phase. The phase-frequency detector produces a phase-frequency detector output proportional to a difference between the reference phase and the feedback phase. A charge pump, coupled to the phase-frequency detector, outputs a charge pump output in response to the phase-frequency detector output. A loop filter, coupled to the charge pump, filters the charge pump output to produce a control voltage. A bias generator is coupled to the loop filter to generate a bias signal to bias the charge pump, causing the charge pump to generate a bias voltage substantially equivalent to the control voltage. The bias voltage is sufficient to cause the charge pump to output substantially zero current when the reference phase substantially equals the feedback phase. A voltage-controlled element, coupled to the phase-frequency detector and the bias generator, is controlled by the control voltage to modify the feedback signal having the feedback phase such that the feedback phase and the reference phase are substantially aligned. The invention may be implemented as part of a multiple loop apparatus including a first loop to generate a first loop output signal having a frequency that is substantially equal to an integral multiple, N, of the frequency of the input signal and a second loop, coupled to the first loop, to generate a second loop output signal from said first loop output signal, wherein the second loop output signal is substantially in phase with the input signal and has a frequency substantially equal to the integer multiple, N, of the frequency of the input signal.

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