Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-07-07
2000-01-11
Thomas, Tom
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438655, 438660, 438663, 438664, 438682, 438685, 257288, 257368, 257382, 257384, 257388, 257412, H01L 21335, H01L 21336, H01L 2176, H01L 21762
Patent
active
060135697
ABSTRACT:
Silicidation of a polysilicon line having frcc upper sidewalls is performed so that no stress is applied to the sidewalls of the polysilicon line, resulting in the formation of a reduced stress silicide structure. This is accomplished by forming a polysilicon line having spacers on either side which extend above the upper surface of the polysilicon line but which are spaced from the edge of the polysilicon line. A layer of a metal such as titanium or tungsten is provided in contact with the top surface polysilicon line. The structure is annealed to cause the metal to react with the polysilicon to form a layer of silicide. Since the upper side portions of the polysilicon line are spaced away from the spacers during the silicidation anneal, the growing silicide region has room to expand without being subjected to lateral stresses in the silicidation process. The suicide is formed in a reduced stress condition, as compared to conventional processes, so that the silicide layer produced will be more readily converted to the desired low resistivity phase of silicide.
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Lin Tony
Lur Water
Souw Bernard E.
Thomas Tom
United Microelectronics Corp.
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