Semiconductor device using a shallow trench isolation

Details Semiconductor device using a shallow trench isolation Semiconductor device using a shallow trench isolation

1997-08-22

1999-11-09

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257510, H01L 2976

Patent

active

059820080

ABSTRACT:
In a MOS transistor using shallow trench isolation, a patten of an element formation region has a shape of a modified hexagon in which a hexagon is compressed into a shape like a rhombus in a direction perpendicular to an extension direction of a gate electrode wiring. The pattern of element formation region is constructed as described above, so that an element formation region is formed in a lager current path in a corner device. Thus, a lowering of a threshold voltage (a short channel effect) due to the corner device can be restricted without increasing a width of the gate electrode wiring.

REFERENCES:
patent: 5378906 (1995-01-01), Lee
patent: 5539229 (1996-07-01), Noble, Jr. et al.
patent: 5567553 (1996-10-01), Hsu et al.
patent: 5702976 (1997-12-01), Shuegraf et al.
patent: 5732009 (1998-03-01), Tadaki et al.
patent: 5741738 (1998-04-01), Mandelman et al.
patent: 5798544 (1998-08-01), Ohya et al.
IEEE Transactions on Electron Devices, vol. 36, No. 9 Sep. 1989. Effects of a New Trench-Isolated Trasistor Using Sidewall Gates. Kazumasa Hieda et al .

Affiliated with

Also associated with

Rating

Semiconductor device using a shallow trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device using a shallow trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device using a shallow trench isolation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1460201