Semiconductor memory device, method of manufacturing the same an

Details Semiconductor memory device, method of manufacturing the same an Semiconductor memory device, method of manufacturing the same an

1996-02-26

1999-11-09

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 58, 257 67, 257903, H01L 27108

Patent

active

059819901

ABSTRACT:
In a memory cell of an SRAM, a load transistor has a pair of source/drain regions formed to define a channel region, and a gate electrode layer being opposite to the channel region with an insulating layer therebetween. A VVP layer is formed to sandwich the channel region with the gate electrode layer to be opposite to channel region with an insulating layer therebetween. This VVP layer is provided such that GND potential is applied when active and Vcc potential is applied during standby. Thus, a large ON current can be implemented while maintaining a small OFF current of a TFT, even when the power supply voltage is made lower due to reduction in voltage.

REFERENCES:
patent: 5281843 (1994-01-01), Ochii et al.
patent: 5557231 (1996-09-01), Yamaguchi et al.

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