Method of fabricating a salicide layer of a device electrode

Details Method of fabricating a salicide layer of a device electrode Method of fabricating a salicide layer of a device electrode

1997-03-11

1999-11-09

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438655, 438656, 438657, 438660, 438664, 438683, 438684, 438652, 438592, 438574, 438579, H01L 2170

Patent

active

059813830

ABSTRACT:
Salicide (self-aligned silicide) structures are formed using a process that does not form oxide spacer structures alongside polysilicon gate electrodes and wiring lines. A shaped polysilicon electrode is formed having protrusions extending beyond the sidewalls of the electrode. LDD source/drain regions are formed by ion implantation using only the polysilicon gate electrode as a mask, thereby forming LDD source drain/regions without using spacer oxide regions. Physical vapor deposition is used to deposit a metal layer having discontinuities at or adjacent the protrusions. A first rapid thermal anneal is performed to cause the metal to form a metal silicide over the polysilicon electrode. Unreacted metal is etched and then a second rapid thermal anneal is performed to convert the metal silicide to its lowest resistivity phase. Gate electrodes and wiring lines having this structure generally are formed having lower stress in the silicide layers, producing salicide structures having lower resistance than gate electrodes and wiring lines formed using conventional salicide techniques.

REFERENCES:
patent: 4818715 (1989-04-01), Chao
patent: 5162884 (1992-11-01), Liou et al.
patent: 5196357 (1993-03-01), Boardman et al.
patent: 5214305 (1993-05-01), Huang et al.
patent: 5518942 (1996-05-01), Shrivastava
patent: 5646056 (1997-07-01), Lin et al.
patent: 5656546 (1997-08-01), Chen et al.
patent: 5753559 (1998-05-01), Yew et al.
Ho, et al., Formation of Self-Aligned TiSi.sub.2 for Very Large Scale Integrated Contacts and Interconnects, J. Vacuum Science and Technology 1396-1401 (1987).
Inoue, et al., A New Cobalt Salicide Technology for 0.15 .mu.m CMOS Using High-Temperature Sputtering and In-Situ Vacuum Annealing, proceedings of the IEDM 18.1 1-4 (1995).
Ohguro, et al., Nitrogen-Doped Nickel Monosilicide Technique for Deep Submicron CMOS Salicide, Proceedings of the IEDM 18.3 1-4 (1995).

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