Semiconductor memory device technical field

Details Semiconductor memory device technical field Semiconductor memory device technical field

1981-02-20

1983-07-05

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

G11C 700

Patent

active

043922112

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION



BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including a redundancy memory cell array therein.
A semiconductor memory device comprises a large number of memory cells arranged along rows and columns which are orthogonal to each other. The density of defects generated in such a semiconductor memory device during manufacturing is relatively independent of the integration density of the device, but is dependent on semiconductor manufacturing technology. Therefore, the higher the integration density of the device is, the greater is the ratio of the number of normal memory cells to that of defective momory cells. This is one of the advantages obtained by increasing the integration density of a semiconductor memory device. However, even if the device includes only one defective memory cell therein, the device cannot operate normally, and therefore the device is abandoned.
In order to be able to operate a semiconductor memory device despite such a defective memory cell, a semiconductor memory device has been known in which a redundancy memory cell array is incorporated with a main memory cell matrix along rows or columns thereof. In this device, when a defective memory cell is detected, the redundancy memory cell array is used instead of a row memory cell array or a column memory cell array including said memory cell. In a semiconductor memory device including such a redundancy memory cell array therein, the manufacturing yield thereof can be improved.
One conventional semiconductor memory device including a redundancy memory cell array comprises a connection area for connecting a redundancy memory cell array to one of the row memory cell arrays of a main memory cell matrix. When a row memory cell array having a defective memory cell is detected, the connections between the defective row memory cell array and a row address decoder are cut off and, after that, the redundancy memory cell array is connected to said row decoder by arranging connections in the connection area. However, in this device, such a cutting off and connecting operation is complex, inefficient and expensive.
Another semiconductor memory device including a redundancy memory cell array therein comprises row address decorders (or column address decorders) each of which has a switching circuit for selecting the redundancy memory cell array (Ref.: IEEE Trans. Electron Devices, vol. ED-26, No. 6, pp. 853-860, June 1979). When a defective memory cell is detected in a row memory cell array, a row address decoder selects the redundancy memory cell array instead of said row memory cell array when the decoder receives a row address signal indicating said row memory cell array. It should be noted that the switching circuit is comprised of a programmable read-only memory (which is a so-called PROM) written by laser light or written electrically. However, in this device, the row address decoders should be comprised of the above-mentioned switching circuits whose number is the same as that of the rows of a main memory cell matrix, which necessitates a complex structure.
Still another conventional semiconductor memory device including a redundancy memory cell array comprises means for comparing one part of an address information such as a row address information with a row address indicating a row memory cell array including a defective memory cell, said row address being given from external terminals, and a switching means for preventing said row address information from being supplied to row address decoders when receiving a coincidence signal generated from the comparing means (Ref. Japanese Patent Laid-Open Application No. Sho. 52-61933). The coincidence signal also serves as a signal for selecting the redundancy memory cell array. In this device, instead of providing the above-mentioned PROM for storing a row address of a defective row memory array, said row address is represented by a combination of connections between the external termi

REFERENCES:
patent: 3753244 (1973-08-01), Sumilas et al.
patent: 4047163 (1977-09-01), Choate et al.
patent: 4365319 (1982-12-01), Takemae

Affiliated with

Also associated with

Rating

Semiconductor memory device technical field does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device technical field, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device technical field will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1443316