Redundancy scheme for an MOS memory

Details Redundancy scheme for an MOS memory Redundancy scheme for an MOS memory

1980-06-30

1982-08-24

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 800, G11C 2900, G11C 1140

Patent

active

043464599

ABSTRACT:
A redundancy scheme is described for use with an MOS memory having a main array of memory cells, and a plurality of spare memory cells. Typically, each memory cell is tested for operability by a conventional probe test. When a defective memory cell is found, an on-chip address controller responds to the probe test finding a defective cell by permanently storing and rendering continuously available a fully asynchronous electrical indication of the address of the defective cell. The address controller compares its stored data with memory cell information received during normal memory operation, and generates a control signal indicative of the receipt of an address which corresponds to a defective cell. A spare cell selector responds to the control signal by electrically accessing a spare memory cell and by prohibiting access of the defective memory cell.

REFERENCES:
patent: 4250570 (1981-02-01), Tsang et al.

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