Method for gate electrode fabrication and symmetrical and non-sy

Details Method for gate electrode fabrication and symmetrical and non-sy Method for gate electrode fabrication and symmetrical and non-sy

1986-03-17

1988-04-12

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156643, 156653, 156656, 156657, 156662, 357 2311, 357 41, 357 55, 437 41, 437 61, 437228, H01L 2978, H01L 2100, H01L 21306, B44C 122, C23F 102

Patent

active

047378280

ABSTRACT:
An edge defining method is employed in the fabrication of narrow electrical patterns for VLSI circuits. The method is particularly employable in the formation of inlay MOSFET transistors having extremely narrow gate widths. The method is also particularly amenable to the fabrication of both symmetrical and non-symmetrical MOSFET devices on the same VLSI circuit chip. The inlay transistor structure is also employed to fabricate NOR and NAND type "ladder" networks and to join vertically and horizontally adjacent semiconductor devices.

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Chow, T. Paul, "Advanced Devices Structures Fabricated with Anisotropic Dry Etching", VLSI Electronics: Microstructure Science, vol. 8, 1984, pp. 487-508.
Woerlee, P. H. et al., "Novel Method of Producing Ultrasmall Platinum Silicide Gate Electrodes", Applied Physics Letters, 47(7), Oct. 1985, pp. 700-702.
Busta, H. H. et al., "Formation of Ultrathin Tungsten Filaments via Selective Low-Pressure Chemical Vapor Deposition", Journal of Applied Physics, 58(2), Jul. 1985, pp. 987-989.

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