Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Measuring or testing
Patent
1989-10-26
1990-12-18
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Measuring or testing
368118, 328 72, 375118, 377 55, G04F 1004
Patent
active
049791770
ABSTRACT:
A logic analyzer has a counter/timer that can reconstruct the higher resolution with which data was acquired using multiple phases of the logic analyzer system clock signal. For a two-phase data sampling system, separate pairs of event recognizers monitor the data collected using the two phases of the system clock. Counter/timer control logic uses the information from these separate pairs of event recognizers to control the behavior of the counter/timer so that it can either single count or double count, depending on whether an event was true during both phases or only one phase of the data acquisition, thus allowing the counter/timer resolution to be as high as the information inherent in the data acquired using both clock phases. The counter/timer employed is capable of single or double counting and has two stages, a prescaler and an extension counter/timer, for increased power and cost effectiveness. An event recognizer is capable of recognizing words, ranges, unstable data, glitches, and/or other signal characteristics.
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Tektronix, 1240/1241 Logic Analyzer Service Manual, 1985, pp. 4-57, to 4-72, and Schematics 18, 18A, 22-25.
Tektronix, 92A16/16E User's Manual, 1987, pp. 2-31, to 2-54.
Griffith Boulden G.
Heyman John S.
Tektronix Inc.
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