DRAM cell array with dynamic gain memory cells

Details DRAM cell array with dynamic gain memory cells DRAM cell array with dynamic gain memory cells

1996-09-26

1998-12-29

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257330, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

058545000

ABSTRACT:
A dynamic gain memory cell of a DRAM cell array includes a planar MOS transistor as a selection transistor and a vertical MOS transistor as a memory transistor, which are connected to one another via a common source/drain region. The memory transistor has a gate electrode of doped silicon, which is disposed along at least one side of a trench. In the trench, an oppositely doped silicon structure is provided, which with the gate electrode of the memory transistor forms a diode, which is connected to the common source/drain region via a contact.

REFERENCES:
patent: 5113235 (1992-05-01), Tamakoshi
patent: 5308783 (1994-05-01), Krautschneider et al.
patent: 5327374 (1994-07-01), Krautschneider et al.
patent: 5559357 (1996-09-01), Krivokapic
patent: 5661322 (1997-08-01), Williams et al.
"Fully Scalable Gain Memory Cell for Future Drams" (Krautschneider et al.), Microelectronic Engineering 15, 1991, pp. 367-370, Elsevier.
"Planar Gain Cell for Low Voltage Operation and Gigabit Memories" Krautschneider et al., 1995 Symposium on VLSI Technology, Siemens AG Corporate Research and Development.

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