Local interconnect process for integrated circuits

Details Local interconnect process for integrated circuits Local interconnect process for integrated circuits

1989-05-31

1990-12-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437192, 437200, 437 41, 148DIG19, 148DIG20, 148DIG15, 357 71, H01L 21283, H01L 21336

Patent

active

049786377

ABSTRACT:
A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.

REFERENCES:
patent: 4470189 (1984-09-01), Roberts et al.
patent: 4640738 (1987-02-01), Fredericke et al.
patent: 4690730 (1987-09-01), Tanj et al.
patent: 4740484 (1988-04-01), Norstrom et al.
patent: 4774204 (1988-09-01), Havemann

Affiliated with

Also associated with

Rating

Local interconnect process for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Local interconnect process for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Local interconnect process for integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1425627