Integrated circuit having horizontally and vertically offset int

Details Integrated circuit having horizontally and vertically offset int Integrated circuit having horizontally and vertically offset int

1996-06-05

1998-12-29

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438669, 438700, 438624, H01L 2144

Patent

active

058541314

ABSTRACT:
An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.

REFERENCES:
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patent: 5506450 (1996-04-01), Lee, et al.
patent: 5565384 (1996-10-01), Havemann
patent: 5733797 (1998-03-01), Yamaha
Patent Abstracts of Japan, vol. 016, No. 360 (E-1243), Aug. 4, 1992 & JP 04 113625 A (Mitsubishi Electric Corp.), Apr. 15, 1992.
International Search Report for PCT/US 97/02329 mailed Jun. 1997.
Wolf, S, "Silicon Processing for the VLSI Era vol. 2", Lattice Press, Calif. 1990 pp. 230-254.
S. Wolf and R. N. Tauber "Silicon Processing for the VLSI Era vol. 1", Lattice press, Calif. pp. 547-549, 1986.

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