Single chamber via etch through a dual-layer dielectric

Details Single chamber via etch through a dual-layer dielectric Single chamber via etch through a dual-layer dielectric

1990-01-03

1990-12-18

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156646, 156653, 156657, 1566591, 20419237, 252 791, 430317, 437203, 437238, 437241, B44C 122, C03C 1500, C03C 2506

Patent

active

049784200

ABSTRACT:
Tapered via holes (10) of uniform diameter are formed in a dual-layer (SiO.sub.2 /SiNi) dielectric (18, 20) used for isolation of metallization layers in an integrated circuit. The method includes forming a photoresist layer (22) atop the nitride layer (20) and patterning the photoresist to define a via hole (24). The nitride and oxide layers are successively plasma etched through the photoresist-defined via holes (24) to form via holes (26, 28) through the dual-layer dielectric to an underlying metal line (16, 17). Etching of the nitride layer is selective to the oxide layer. Etching of the oxide layer is selective to the metal line. The photoresist and nitride layers are etched simultaneously in the presence of oxygen so as to taper the via hole in the nitride. The oxide is etched in the absence of oxygen, producing a tapered sidewall profile (32) extending continuously to the metal.

REFERENCES:
patent: 3474021 (1969-10-01), Davidse et al.
patent: 4376672 (1983-03-01), Wang et al.
patent: 4420504 (1983-12-01), Cooper et al.
patent: 4529476 (1985-07-01), Kawamoto et al.
patent: 4545852 (1985-10-01), Barton
patent: 4568410 (1986-02-01), Thornquist
patent: 4793897 (1988-12-01), Dunfield et al.

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