Threshold adjustment in field effect semiconductor devices

Details Threshold adjustment in field effect semiconductor devices Threshold adjustment in field effect semiconductor devices

1995-06-06

1998-03-10

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257404, H01L 2976

Patent

active

057264775

ABSTRACT:
A process for fabricating both CMOS and LDMOS transistors includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming MOSFET body regions. Similarly, a process for fabricating both CMOS and NPN transistors includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming NPN base regions. In both processes, the threshold voltage of the PMOS devices is adjusted subsequent to both gate formation and the high temperature, long diffusions by implanting a suitable dopant into the PMOS channel through the gate. Since the gate is formed prior to threshold adjust, high temperature processing and long diffusions requiring the presence of the gate are completed without adversely affecting the adjusted threshold voltage. The p+ source/drain implant mask can be used to restrict the threshold adjust implant to the PMOS devices, thereby avoiding adversely affecting other devices in the integrated circuit. The p+ source/drain implant mask can also be used to protect the gates of some of the PMOS devices, thereby fabricating two classes of PMOS devices, one being threshold adjusted and the other not being threshold adjusted. The threshold adjusted devices may be either enhancement or depletion mode.

REFERENCES:
patent: 3461361 (1969-08-01), Delivorias
patent: 3895966 (1975-07-01), MacDougall et al.
patent: 4080718 (1978-03-01), Richman
patent: 4173818 (1979-11-01), Bassous et al.
patent: 4210465 (1980-07-01), Brower
patent: 4212684 (1980-07-01), Brower
patent: 4258378 (1981-03-01), Wall
patent: 4294001 (1981-10-01), Kuo
patent: 4329186 (1982-05-01), Kotecha et al.
patent: 4342100 (1982-07-01), Kuo
patent: 4356042 (1982-10-01), Gedaly et al.
patent: 4472871 (1984-09-01), Green et al.
patent: 4514893 (1985-05-01), Kinsbron et al.
patent: 4525378 (1985-06-01), Schwabe et al.
patent: 4598460 (1986-07-01), Owens et al.
patent: 4737471 (1988-04-01), Shirato et al.
patent: 4764482 (1988-08-01), Hsu
patent: 4845047 (1989-07-01), Holloway et al.
patent: 4866002 (1989-09-01), Shizukuishi et al.
patent: 4889820 (1989-12-01), Mori
patent: 4927776 (1990-05-01), Soejima
patent: 4956311 (1990-09-01), Liou et al.
patent: 4960726 (1990-10-01), Lechaton et al.
patent: 4968639 (1990-11-01), Bergonzoni
patent: 5036019 (1991-07-01), Yamane et al.
patent: 5118633 (1992-06-01), Sagara et al.
patent: 5169794 (1992-12-01), Iranmanesh
J. Y.-C. Sun et al., "Study of Boron Penetration Through Thin Oxide With P+-Polysilicon Date", Digest of Technical Papers, May 1989 Symposium on VLSI Tech., Kyoto, Japan, pp. 17-18.
K.A. Sabine, et al., "Threshold shift of NMOS transistors due to high energy arsenic source/drain implantation", IEEE Proceedings vol. 132, pt. 1, No. 3, Jun. 1985, pp. 163-166.

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