Single event upset hardening CMOS memory circuit

Details Single event upset hardening CMOS memory circuit Single event upset hardening CMOS memory circuit

1990-11-06

1992-05-05

Clawson, Jr., Joseph E.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 365190, 365208, G11C 700

Patent

active

051114291

ABSTRACT:
A CMOS storage cell includes an n-channel storage circuit which has cross coupled n-channel storage transistors and a p-channel storage circuit including cross coupled p-channel storage transistors. Each of the n-channel storage transistors has an n-channel load transistor and each of the p-channel storage transistors has a p-channel load transistor. The n-channel load transistors are coupled to be controlled by the p-channel storage circuit and the p-channel load transistors are coupled to be controlled by the n-channel storage circuit. The n-channel load transistors are designed to carry less current than the p-channel storage transistors and the p-channel load transistors are designed to carry less current than the n-channel storage transistors. The storage cell can be used for a Static RAM or for a flip flop.

REFERENCES:
patent: 4782467 (1988-11-01), Belt et al.
patent: 4805148 (1989-02-01), Diehl-Nagle et al.
patent: 5043939 (1991-08-01), Slamowitz et al.

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